1. Field of the Invention
This invention relates to integrated circuit structures. More particularly this invention relates to the formation of a low dielectric constant (k) fluorine and carbon-containing silicon oxide dielectric material for use in the formation of integrated circuit structures.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
Dobson et al., in an article entitled “Advanced SiO2 Planarization Using Silane and H2O2”, published in Semiconductor International, December 1994, at pages 85-88, describe the low temperature formation of SiO2 by reaction of silane (SiH4) with hydrogen peroxide (H2O2) to produce a silicon oxide which flows like a liquid and thus exhibits good gap fill characteristics. In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH3—SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Flowfill process.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on February 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H202 to achieve a dielectric constant of ˜2.9.
The incorporation of such carbon-doped silicon oxide dielectric material into interconnect architecture has been very attractive not only because of the low k properties, but also because of the compatibility with conventional silicon process technologies. Generally these materials remain stable upon annealing at temperatures of up to 500° C. The carbon doped silicon oxide materials are characterized by the structure of amorphous silicon oxide with incorporated methyl groups and hydrogen species, and are also characterized by a reduced density in comparison with conventional silicon oxide that can be explained by the formation of microporosity surrounding the incorporated methyl groups. Furthermore, such hydrocarbon-modified silicon oxide dielectric materials deposited by CVD techniques are also characterized by strong adhesion.
While such carbon-doped silicon oxide dielectric materials do exhibit the desired low k (i.e., dielectric constants below about 3.0), resulting in reduced capacitance of the dielectric material, a major problem of such carbon-doped silicon oxide is a low resistance to oxidation during subsequent processing steps that results in a destruction of the incorporated hydrocarbons and a resulting increase in the overall dielectric constant of the dielectric material. The sensitivity to oxidation is thought to be due to the reactivity of the C—H bonds of the methyl group bonded to silicon. The unintended removal of the methyl group results in a more hydrophilic surface that may be responsible for a so-called “via poisoning” which is observed after via etch and photoresist strip with oxygen-containing plasma, and is related to suppression of the surface nucleation in subsequent via liner deposition steps.
More recently, Sugahara et al., in an article entitled “Chemical Vapor Deposition of CF3-Incorporated Silica Films for Interlayer Dielectric Applications”, published in the 1999 Joint International Meeting, Electrochemical Society Meeting Abstracts, volume 99-2, Abstract 746, 1999, described the reaction of trimethyl-fluoromethyl-silane (CF3Si(CH3)3) with an ozone oxidizer at an elevated temperature. Sugahara et al. stated that the low reactivity of Si-alkyl bonds required the deposition to be carried at elevated temperatures (˜350° C.). The dielectric material formed by the reaction demonstrated resistance to oxidation by oxygen plasma. However, the precursor compound used by Sugahara yielded only approximately 15% CF3 content in the product dielectric layer. Further, it is known that dielectric films produced by high temperature ozone processes are characterized by poor gap-fill, while continuous shrinkage in feature size of integrated circuit structure demands an increased gap-fill capability.
It would, therefore, be desirable to provide a process for forming a low k silicon oxide dielectric material using precursor compounds that can provide greater control of the amount of organofluoro moieties incorporated into the dielectric material. It would also be desirable to provide, in at least one embodiment, a low k silicon oxide dielectric material which exhibits the gap-fill properties and film adherence properties of CVD-formed low k carbon doped silicon oxide dielectric materials such as discussed by the Dobson et al., Peters, and McClatchie et al. articles discussed above, while also maintaining a low formation temperature to conserve the thermal budget of the integrated circuit structure. This invention provides these characteristics and provides additional advantages as well.